(1) Field of the Invention
This invention relates to a CMOS image sensor for getting images by outputting in order image signals sensed in each of pixel areas arranged like a matrix on the basis of X-Y addressing.
(2) Description of the Related Art
With the spread of digital still-image cameras and digital video cameras, the addition of a camera function to cellular telephones, and the like, a demand for solid imaging devices has risen in recent years. At present charge coupled devices (CCDs) have spread most widely as solid imaging devices. However, these CCDs have the drawbacks of the need of a plurality of power supply circuits, a high driving voltage, and high power consumption. Therefore, attention has recently been riveted to CMOS image sensors which can be produced by the process for producing complementary metal-oxide semiconductors (CMOSes), which can operate at a low voltage, which consume only a small amount of power, and the unit cost of the production of which is low.
In CMOS image sensors, pixel circuits each of which gets an image corresponding to one pixel are arranged like a matrix. They output image signals corresponding to an entire image by selecting in order output from each pixel circuit with a vertical scanning shift register and horizontal scanning shift register.
FIG. 7 is a view showing the structure of a pixel circuit in a conventional CMOS image sensor.
A pixel circuit 70 shown in FIG. 7 includes a photodiode D71 as a photoelectric conversion element and has an active pixel sensor (APS) structure in which a reset transistor M71, source follower amplifier M72, and row selection transistor M73 each formed by, for example, an n-channel MOS field-effect transistor (MOSFET) are located.
The anode side of the photodiode D71 is grounded and the cathode side is connected to a source electrode on the reset transistor M71 and a gate electrode on the source follower amplifier M72. A drain electrode on the reset transistor M71 and a drain electrode on the source follower amplifier M72 are connected to a power supply line L71 where reset voltage VR is supplied. A gate electrode on the reset transistor M71 is connected to a reset signal line L72 where a reset signal RST is supplied.
A source electrode on the source follower amplifier M72 is connected to a drain electrode on the row selection transistor M73. A gate electrode on the row selection transistor M73 is connected to a row selection signal line L73 where a row selection signal SLCT for selecting the pixel circuit 70 in a row direction is supplied. A source electrode on the row selection transistor M73 is connected to a column selection signal line L74 for selecting the pixel circuit 70 in a column direction.
Operation in the pixel circuit 70 will now be described in brief. First, the photodiode D71 is charged by reset voltage VR when the reset transistor M71 goes into the ON state with predetermined timing due to a reset signal RST. Next, when light strikes it, the photodiode D71 begins to discharge and its potential drops from the reset voltage VR. After a predetermined period of time elapsed, a row selection signal SLCT is input to the gate electrode on the row selection transistor M73. When the row selection transistor M73 goes into the ON state, the voltage of the source of the source follower amplifier M72 is gotten as a signal voltage via the column selection signal line L74.
The column selection signal line L74 is connected to, for example, a drain electrode on a column selection transistor (not shown) via an amplifier/noise cancel circuit (not shown). In a CMOS image sensor, each of the pixel circuits 70 arranged in a horizontal direction is selected by a row selection signal SLCT, the column selection transistors each connected to the column selection signal line L74 are put in order into the ON state, and image signals corresponding to one pixel are output in order.
By the way, with CMOS image sensors having the above APS structure, reset noise produced at the source electrode on the reset transistor M71 at the time of a reset signal RST being put into the OFF state will degrade output image signals. The pixel circuits 70 differ from one another in this reset noise due to, for example, variation in threshold voltage VT for the reset transistors M71. Conventionally, correlated double sampling (CDS) circuits have been used to reduce this reset noise.
A CDS circuit is located in each column in the amplifier/noise cancel circuit connected to each column selection signal line L74. The relation between the operation of this CDS circuit and each pixel circuit 70 is as follows. A signal voltage output from the pixel circuit 70 is sampled first by the CDS circuit. Then the photodiode D71 in the pixel circuit 70 is reset to reset voltage VR and voltage output from the pixel circuit 70 at the time of a reset is sampled by the CDS circuit. And then the difference between the voltage output at the time of a reset and signal voltage is calculated. This cancels out reset noise and only image signals can be extracted.
By the way, with CMOS image sensors, the integration level of circuits is getting high due to demands for high resolution. However, a high integration level will lead to a narrow space between signal wirings. As a result, interference will occur between signals transmitted over adjacent signal wirings due to parasitic capacitance. If this interference is significant, distinct images cannot be gotten.
As described above, a CDS circuit for reducing reset noise is located in each column. FIG. 8 is a view for intelligibly describing how to locate CDS circuits in circuits in a conventional CMOS image sensor.
As shown in FIG. 8, CDS circuits 80 are arranged in a horizontal direction in the same way as the column selection signal lines L74 located parallel to one another by n columns in a horizontal direction. The input side of each CDS circuit 80 is connected to an output section of each pixel circuit 70 via each column selection signal line L74 and the output side is connected to, for example, a drain electrode on each column selection transistor (not shown).
Usually each CDS circuit 80 has the same wiring pattern. Therefore, if the CDS circuits 80 are located parallel to one another in this way, a portion of a signal transmission wiring for transmitting a signal output from the pixel circuit 70 which is located parallel to a signal transmission wiring in an adjacent CDS circuit 80 increases. Therefore, if a high integration level leads to a narrow space between the CDS circuits 80, image signals from pixels adjacent to each other in a horizontal direction will interfere due to parasitic capacitance between the signal transmission wirings. For example, if there are an area with strong brightness and an area with dim brightness on an image gotten, the border between these areas may not be displayed distinctly.
Conventionally, interference between adjacent image signals has been controlled by increasing the capacitance of a capacitive element for sampling included in the CDS circuit 80. Alternatively, the interference has been controlled by increasing operating current for an amplifier located in the CDS circuit 80. With these methods, however, the size of CDS circuits becomes large and consumption of power increases.